wut
v1.7.0
Wii U Toolchain
include
coreinit
performancemonitor.h
Go to the documentation of this file.
1
#pragma once
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#include <
wut.h
>
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12
#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
enum
OSPerfMonArg
{
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OS_PM_ARG_MMCR0
= 1u << 0u,
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OS_PM_ARG_MMCR1
= 1u << 1u,
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OS_PM_ARG_PMC1
= 1u << 2u,
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OS_PM_ARG_PMC2
= 1u << 3u,
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OS_PM_ARG_PMC3
= 1u << 4u,
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OS_PM_ARG_PMC4
= 1u << 5u,
25
}
OSPerfMonArg
;
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typedef
enum
OSPerfMonMMCR0Flags
{
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OS_PM_MMCR0_PMC1_CURRENT
= 0b0000000u << 6,
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OS_PM_MMCR0_PMC1_CPU_CYCLES
= 0b0000001u << 6,
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OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED
= 0b0000010u << 6,
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OS_PM_MMCR0_PMC1_TBL_RISING_TRANSITIONS
= 0b0000011u << 6,
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OS_PM_MMCR0_PMC1_INSTRUCTIONS_DISPATCHED
= 0b0000100u << 6,
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OS_PM_MMCR0_PMC1_EIEIO_INSTRUCTIONS_COMPLETED
= 0b0000101u << 6,
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OS_PM_MMCR0_PMC1_ITLB_SEARCH_CYCLES
= 0b0000110u << 6,
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OS_PM_MMCR0_PMC1_L2_HITS
= 0b0000111u << 6,
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OS_PM_MMCR0_PMC1_INSTRUCTIONS_EA_DELIVERED
= 0b0001000u << 6,
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OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED_MATCHES_IABR
= 0b0001001u << 6,
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OS_PM_MMCR0_PMC1_SLOW_L1_MISSES
= 0b0001010u << 6,
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OS_PM_MMCR0_PMC1_UNRESOLVED_BRANCHES
= 0b0001011u << 6,
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OS_PM_MMCR0_PMC1_UNRESOLVED_STALL_CYCLES
= 0b0001100u << 6,
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OS_PM_MMCR0_PMC1_L1_SHARED_STORES
= 0b0001110u << 6,
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OS_PM_MMCR0_PMC1_L2_SHARED_INTERVENTIONS
= 0b0001111u << 6,
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OS_PM_MMCR0_PMC1_CACHE_PARADOXES
= 0b0010000u << 6,
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OS_PM_MMCR0_PMC1_CIU_LOAD_REQUESTS
= 0b0010100u << 6,
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OS_PM_MMCR0_PMC1_BIU_ADDRESS_ONLY_REQUESTS
= 0b0010101u << 6,
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OS_PM_MMCR0_PMC1_CIU_PARADOXES
= 0b0010110u << 6,
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OS_PM_MMCR0_PMC1_60XE_BUS_DATA_BEATS
= 0b0010111u << 6,
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OS_PM_MMCR0_PMC2_CURRENT
= 0b000000u,
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OS_PM_MMCR0_PMC2_CPU_CYCLES
= 0b000001u,
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OS_PM_MMCR0_PMC2_INSTRUCTIONS_COMPLETED
= 0b000010u,
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OS_PM_MMCR0_PMC2_TBL_RISING_TRANSITIONS
= 0b000011u,
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OS_PM_MMCR0_PMC2_INSTRUCTIONS_DISPATCHED
= 0b000100u,
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OS_PM_MMCR0_PMC2_L1_ICACHE_MISSES
= 0b000101u,
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OS_PM_MMCR0_PMC2_ITLB_MISSES
= 0b000110u,
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OS_PM_MMCR0_PMC2_L2_INSTRUCTION_MISSES
= 0b000111u,
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OS_PM_MMCR0_PMC2_PRED_BRANCHES_NOT_TAKEN
= 0b001000u,
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OS_PM_MMCR0_PMC2_RESERVED_LOADS
= 0b001010u,
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OS_PM_MMCR0_PMC2_LOADS_AND_STORES
= 0b001011u,
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OS_PM_MMCR0_PMC2_CACHE_SNOOPS
= 0b001100u,
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OS_PM_MMCR0_PMC2_L1_TO_L2_CASTOUTS
= 0b001101u,
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OS_PM_MMCR0_PMC2_SYSTEM_UNIT_INSTRUCTIONS
= 0b001110u,
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OS_PM_MMCR0_PMC2_L1_INSTRUCTION_MISS_CYCLES
= 0b001111u,
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OS_PM_MMCR0_PMC2_FIRST_SPECULATIVE_BRANCH_RESOLVES
= 0b010000u,
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OS_PM_MMCR0_PMC2_L2_SHARED_STORES
= 0b010001u,
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OS_PM_MMCR0_PMC2_L1_SHARED_INTERVENTIONS
= 0b010010u,
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OS_PM_MMCR0_PMC2_CIU_STORE_REQUESTS
= 0b010100u,
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OS_PM_MMCR0_PMC2_SLOW_OUTSTANDING_BIU_TRANSACTIONS
= 0b010101u,
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OS_PM_MMCR0_PMC2_CIU_MODIFIED_INTERVENTIONS
= 0b010110u,
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}
OSPerfMonMMCR0Flags
;
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typedef
enum
OSPerfMonMMCR1Flags
{
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OS_PM_MMCR1_PMC3_CURRENT
= 0b00000u << 27,
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OS_PM_MMCR1_PMC3_CPU_CYCLES
= 0b00001u << 27,
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OS_PM_MMCR1_PMC3_INSTRUCTIONS_COMPLETED
= 0b00010u << 27,
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OS_PM_MMCR1_PMC3_TBL_RISING_TRANSITIONS
= 0b00011u << 27,
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OS_PM_MMCR1_PMC3_INSTRUCTIONS_DISPATCHED
= 0b00100u << 27,
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OS_PM_MMCR1_PMC3_L1_DCACHE_MISSES
= 0b00101u << 27,
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OS_PM_MMCR1_PMC3_DTLB_MISSES
= 0b00110u << 27,
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OS_PM_MMCR1_PMC3_L2_DATA_MISSES
= 0b00111u << 27,
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OS_PM_MMCR1_PMC3_PRED_BRANCHES_TAKEN
= 0b01000u << 27,
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OS_PM_MMCR1_PMC3_COND_STORES_COMPLETED
= 0b01010u << 27,
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OS_PM_MMCR1_PMC3_FPU_INSTRUCTIONS_COMPLETED
= 0b01011u << 27,
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OS_PM_MMCR1_PMC3_L2_CASTOUTS_BY_SNOOPS
= 0b01100u << 27,
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OS_PM_MMCR1_PMC3_L2_CACHE_OPERATIONS
= 0b01101u << 27,
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OS_PM_MMCR1_PMC3_L1_LOAD_MISS_CYCLES
= 0b01111u << 27,
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OS_PM_MMCR1_PMC3_SECOND_SPECULATIVE_BRANCH_RESOLVES
= 0b10000u << 27,
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OS_PM_MMCR1_PMC3_BPU_STALL_LR_CR_CYCLES
= 0b10001u << 27,
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OS_PM_MMCR1_PMC3_L1_MODIFIED_INTERVENTIONS
= 0b10010u << 27,
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OS_PM_MMCR1_PMC3_ICBI_SNOOPS
= 0b10011u << 27,
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OS_PM_MMCR1_PMC3_CIU_ADDRESS_ONLY_REQUESTS
= 0b10100u << 27,
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OS_PM_MMCR1_PMC3_BIU_LOAD_REQUESTS
= 0b10101u << 27,
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OS_PM_MMCR1_PMC3_CIU_SHARED_INTERVENTIONS
= 0b10110u << 27,
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OS_PM_MMCR1_PMC4_CURRENT
= 0b00000u << 22,
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OS_PM_MMCR1_PMC4_CPU_CYCLES
= 0b00001u << 22,
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OS_PM_MMCR1_PMC4_INSTRUCTIONS_COMPLETED
= 0b00010u << 22,
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OS_PM_MMCR1_PMC4_TBL_RISING_TRANSITIONS
= 0b00011u << 22,
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OS_PM_MMCR1_PMC4_INSTRUCTIONS_DISPATCHED
= 0b00100u << 22,
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OS_PM_MMCR1_PMC4_L2_CASTOUTS
= 0b00101u << 22,
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OS_PM_MMCR1_PMC4_DTLB_SEARCH_CYCLES
= 0b00110u << 22,
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OS_PM_MMCR1_PMC4_BRANCHES_MISPREDICTED
= 0b01000u << 22,
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OS_PM_MMCR1_PMC4_INTACT_COND_STORES_COMPLETED
= 0b01010u << 22,
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OS_PM_MMCR1_PMC4_SYNC_INSTRUCTIONS_COMPLETED
= 0b01011u << 22,
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OS_PM_MMCR1_PMC4_SNOOP_RETRIES
= 0b01100u << 22,
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OS_PM_MMCR1_PMC4_INTEGER_OPERATIONS
= 0b01101u << 22,
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OS_PM_MMCR1_PMC4_BPU_STALL_TWO_BRANCHES_CYCLES
= 0b01110u << 22,
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OS_PM_MMCR1_PMC4_L2_MODIFIED_INTERVENTIONS
= 0b10000u << 22,
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OS_PM_MMCR1_PMC4_TLBIE_SNOOPS
= 0b10001u << 22,
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OS_PM_MMCR1_PMC4_L2_BANK_REFRESH_OVERFLOWS
= 0b10010u << 22,
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OS_PM_MMCR1_PMC4_CIU_ARTRY_COUNT
= 0b10100u << 22,
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OS_PM_MMCR1_PMC4_BIU_STORE_REQUESTS
= 0b10101u << 22,
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OS_PM_MMCR1_PMC4_CIU_TWO_CORE_SHARED_INTERVENTIONS
= 0b10110u << 22,
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}
OSPerfMonMMCR1Flags
;
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void
OSSetPerformanceMonitor
(uint32_t arg_mask,
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uint32_t mmcr0,
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uint32_t mmcr1,
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uint32_t pmc1,
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uint32_t pmc2,
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uint32_t pmc3,
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uint32_t pmc4);
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static
inline
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uint32_t
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OSGetUPMC1
()
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{
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uint32_t result;
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asm
(
"mfupmc1 %[result]"
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: [result]
"=r"
(result));
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return
result;
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}
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static
inline
167
uint32_t
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OSGetUPMC2
()
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{
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uint32_t result;
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asm
(
"mfupmc2 %[result]"
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: [result]
"=r"
(result));
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return
result;
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}
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static
inline
180
uint32_t
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OSGetUPMC3
()
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{
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uint32_t result;
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asm
(
"mfupmc3 %[result]"
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: [result]
"=r"
(result));
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return
result;
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}
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static
inline
193
uint32_t
194
OSGetUPMC4
()
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{
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uint32_t result;
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asm
(
"mfupmc4 %[result]"
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: [result]
"=r"
(result));
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return
result;
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}
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#ifdef __cplusplus
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}
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#endif
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OSGetUPMC4
static uint32_t OSGetUPMC4()
Convenience function to read from UPMC4.
Definition:
performancemonitor.h:194
OSGetUPMC3
static uint32_t OSGetUPMC3()
Convenience function to read from UPMC3.
Definition:
performancemonitor.h:181
OSPerfMonArg
OSPerfMonArg
Used to tell OSSetPerformanceMonitor() which arguments are valid.
Definition:
performancemonitor.h:18
OSSetPerformanceMonitor
void OSSetPerformanceMonitor(uint32_t arg_mask, uint32_t mmcr0, uint32_t mmcr1, uint32_t pmc1, uint32_t pmc2, uint32_t pmc3, uint32_t pmc4)
Write to performance monitor registers.
OSGetUPMC1
static uint32_t OSGetUPMC1()
Convenience function to read from UPMC1.
Definition:
performancemonitor.h:155
OSGetUPMC2
static uint32_t OSGetUPMC2()
Convenience function to read from UPMC2.
Definition:
performancemonitor.h:168
OSPerfMonMMCR1Flags
OSPerfMonMMCR1Flags
Flags to write to (U)MMCR1 register.
Definition:
performancemonitor.h:82
OSPerfMonMMCR0Flags
OSPerfMonMMCR0Flags
Flags to write to (U)MMCR0 register.
Definition:
performancemonitor.h:32
OS_PM_ARG_MMCR0
@ OS_PM_ARG_MMCR0
Definition:
performancemonitor.h:19
OS_PM_ARG_PMC1
@ OS_PM_ARG_PMC1
Definition:
performancemonitor.h:21
OS_PM_ARG_PMC2
@ OS_PM_ARG_PMC2
Definition:
performancemonitor.h:22
OS_PM_ARG_PMC4
@ OS_PM_ARG_PMC4
Definition:
performancemonitor.h:24
OS_PM_ARG_PMC3
@ OS_PM_ARG_PMC3
Definition:
performancemonitor.h:23
OS_PM_ARG_MMCR1
@ OS_PM_ARG_MMCR1
Definition:
performancemonitor.h:20
OS_PM_MMCR1_PMC3_L1_DCACHE_MISSES
@ OS_PM_MMCR1_PMC3_L1_DCACHE_MISSES
Definition:
performancemonitor.h:88
OS_PM_MMCR1_PMC3_SECOND_SPECULATIVE_BRANCH_RESOLVES
@ OS_PM_MMCR1_PMC3_SECOND_SPECULATIVE_BRANCH_RESOLVES
Definition:
performancemonitor.h:97
OS_PM_MMCR1_PMC3_L2_CACHE_OPERATIONS
@ OS_PM_MMCR1_PMC3_L2_CACHE_OPERATIONS
Definition:
performancemonitor.h:95
OS_PM_MMCR1_PMC3_ICBI_SNOOPS
@ OS_PM_MMCR1_PMC3_ICBI_SNOOPS
Definition:
performancemonitor.h:100
OS_PM_MMCR1_PMC3_BPU_STALL_LR_CR_CYCLES
@ OS_PM_MMCR1_PMC3_BPU_STALL_LR_CR_CYCLES
Definition:
performancemonitor.h:98
OS_PM_MMCR1_PMC3_DTLB_MISSES
@ OS_PM_MMCR1_PMC3_DTLB_MISSES
Definition:
performancemonitor.h:89
OS_PM_MMCR1_PMC3_L2_CASTOUTS_BY_SNOOPS
@ OS_PM_MMCR1_PMC3_L2_CASTOUTS_BY_SNOOPS
Definition:
performancemonitor.h:94
OS_PM_MMCR1_PMC3_FPU_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC3_FPU_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:93
OS_PM_MMCR1_PMC3_CPU_CYCLES
@ OS_PM_MMCR1_PMC3_CPU_CYCLES
Definition:
performancemonitor.h:84
OS_PM_MMCR1_PMC4_DTLB_SEARCH_CYCLES
@ OS_PM_MMCR1_PMC4_DTLB_SEARCH_CYCLES
Definition:
performancemonitor.h:111
OS_PM_MMCR1_PMC4_CIU_ARTRY_COUNT
@ OS_PM_MMCR1_PMC4_CIU_ARTRY_COUNT
Definition:
performancemonitor.h:121
OS_PM_MMCR1_PMC3_L1_LOAD_MISS_CYCLES
@ OS_PM_MMCR1_PMC3_L1_LOAD_MISS_CYCLES
Definition:
performancemonitor.h:96
OS_PM_MMCR1_PMC4_L2_BANK_REFRESH_OVERFLOWS
@ OS_PM_MMCR1_PMC4_L2_BANK_REFRESH_OVERFLOWS
Definition:
performancemonitor.h:120
OS_PM_MMCR1_PMC4_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC4_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:107
OS_PM_MMCR1_PMC4_INTACT_COND_STORES_COMPLETED
@ OS_PM_MMCR1_PMC4_INTACT_COND_STORES_COMPLETED
Definition:
performancemonitor.h:113
OS_PM_MMCR1_PMC3_PRED_BRANCHES_TAKEN
@ OS_PM_MMCR1_PMC3_PRED_BRANCHES_TAKEN
Definition:
performancemonitor.h:91
OS_PM_MMCR1_PMC4_CIU_TWO_CORE_SHARED_INTERVENTIONS
@ OS_PM_MMCR1_PMC4_CIU_TWO_CORE_SHARED_INTERVENTIONS
Definition:
performancemonitor.h:123
OS_PM_MMCR1_PMC3_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC3_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:85
OS_PM_MMCR1_PMC4_BRANCHES_MISPREDICTED
@ OS_PM_MMCR1_PMC4_BRANCHES_MISPREDICTED
Definition:
performancemonitor.h:112
OS_PM_MMCR1_PMC3_L1_MODIFIED_INTERVENTIONS
@ OS_PM_MMCR1_PMC3_L1_MODIFIED_INTERVENTIONS
Definition:
performancemonitor.h:99
OS_PM_MMCR1_PMC4_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR1_PMC4_TBL_RISING_TRANSITIONS
Definition:
performancemonitor.h:108
OS_PM_MMCR1_PMC4_L2_CASTOUTS
@ OS_PM_MMCR1_PMC4_L2_CASTOUTS
Definition:
performancemonitor.h:110
OS_PM_MMCR1_PMC3_CURRENT
@ OS_PM_MMCR1_PMC3_CURRENT
Definition:
performancemonitor.h:83
OS_PM_MMCR1_PMC3_COND_STORES_COMPLETED
@ OS_PM_MMCR1_PMC3_COND_STORES_COMPLETED
Definition:
performancemonitor.h:92
OS_PM_MMCR1_PMC3_L2_DATA_MISSES
@ OS_PM_MMCR1_PMC3_L2_DATA_MISSES
Definition:
performancemonitor.h:90
OS_PM_MMCR1_PMC4_CURRENT
@ OS_PM_MMCR1_PMC4_CURRENT
Definition:
performancemonitor.h:105
OS_PM_MMCR1_PMC4_CPU_CYCLES
@ OS_PM_MMCR1_PMC4_CPU_CYCLES
Definition:
performancemonitor.h:106
OS_PM_MMCR1_PMC4_L2_MODIFIED_INTERVENTIONS
@ OS_PM_MMCR1_PMC4_L2_MODIFIED_INTERVENTIONS
Definition:
performancemonitor.h:118
OS_PM_MMCR1_PMC4_TLBIE_SNOOPS
@ OS_PM_MMCR1_PMC4_TLBIE_SNOOPS
Definition:
performancemonitor.h:119
OS_PM_MMCR1_PMC4_BPU_STALL_TWO_BRANCHES_CYCLES
@ OS_PM_MMCR1_PMC4_BPU_STALL_TWO_BRANCHES_CYCLES
Definition:
performancemonitor.h:117
OS_PM_MMCR1_PMC3_BIU_LOAD_REQUESTS
@ OS_PM_MMCR1_PMC3_BIU_LOAD_REQUESTS
Definition:
performancemonitor.h:102
OS_PM_MMCR1_PMC4_INTEGER_OPERATIONS
@ OS_PM_MMCR1_PMC4_INTEGER_OPERATIONS
Definition:
performancemonitor.h:116
OS_PM_MMCR1_PMC3_CIU_SHARED_INTERVENTIONS
@ OS_PM_MMCR1_PMC3_CIU_SHARED_INTERVENTIONS
Definition:
performancemonitor.h:103
OS_PM_MMCR1_PMC3_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR1_PMC3_TBL_RISING_TRANSITIONS
Definition:
performancemonitor.h:86
OS_PM_MMCR1_PMC4_SNOOP_RETRIES
@ OS_PM_MMCR1_PMC4_SNOOP_RETRIES
Definition:
performancemonitor.h:115
OS_PM_MMCR1_PMC4_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR1_PMC4_INSTRUCTIONS_DISPATCHED
Definition:
performancemonitor.h:109
OS_PM_MMCR1_PMC3_CIU_ADDRESS_ONLY_REQUESTS
@ OS_PM_MMCR1_PMC3_CIU_ADDRESS_ONLY_REQUESTS
Definition:
performancemonitor.h:101
OS_PM_MMCR1_PMC4_BIU_STORE_REQUESTS
@ OS_PM_MMCR1_PMC4_BIU_STORE_REQUESTS
Definition:
performancemonitor.h:122
OS_PM_MMCR1_PMC4_SYNC_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC4_SYNC_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:114
OS_PM_MMCR1_PMC3_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR1_PMC3_INSTRUCTIONS_DISPATCHED
Definition:
performancemonitor.h:87
OS_PM_MMCR0_PMC1_CIU_PARADOXES
@ OS_PM_MMCR0_PMC1_CIU_PARADOXES
Definition:
performancemonitor.h:51
OS_PM_MMCR0_PMC2_RESERVED_LOADS
@ OS_PM_MMCR0_PMC2_RESERVED_LOADS
Definition:
performancemonitor.h:63
OS_PM_MMCR0_PMC1_CIU_LOAD_REQUESTS
@ OS_PM_MMCR0_PMC1_CIU_LOAD_REQUESTS
Definition:
performancemonitor.h:49
OS_PM_MMCR0_PMC1_60XE_BUS_DATA_BEATS
@ OS_PM_MMCR0_PMC1_60XE_BUS_DATA_BEATS
Definition:
performancemonitor.h:52
OS_PM_MMCR0_PMC1_CPU_CYCLES
@ OS_PM_MMCR0_PMC1_CPU_CYCLES
Definition:
performancemonitor.h:34
OS_PM_MMCR0_PMC1_L2_HITS
@ OS_PM_MMCR0_PMC1_L2_HITS
Definition:
performancemonitor.h:40
OS_PM_MMCR0_PMC2_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR0_PMC2_TBL_RISING_TRANSITIONS
Definition:
performancemonitor.h:57
OS_PM_MMCR0_PMC2_L1_TO_L2_CASTOUTS
@ OS_PM_MMCR0_PMC2_L1_TO_L2_CASTOUTS
Definition:
performancemonitor.h:66
OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED_MATCHES_IABR
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED_MATCHES_IABR
Definition:
performancemonitor.h:42
OS_PM_MMCR0_PMC2_LOADS_AND_STORES
@ OS_PM_MMCR0_PMC2_LOADS_AND_STORES
Definition:
performancemonitor.h:64
OS_PM_MMCR0_PMC2_ITLB_MISSES
@ OS_PM_MMCR0_PMC2_ITLB_MISSES
Definition:
performancemonitor.h:60
OS_PM_MMCR0_PMC1_UNRESOLVED_BRANCHES
@ OS_PM_MMCR0_PMC1_UNRESOLVED_BRANCHES
Definition:
performancemonitor.h:44
OS_PM_MMCR0_PMC2_L1_INSTRUCTION_MISS_CYCLES
@ OS_PM_MMCR0_PMC2_L1_INSTRUCTION_MISS_CYCLES
Definition:
performancemonitor.h:68
OS_PM_MMCR0_PMC2_L2_INSTRUCTION_MISSES
@ OS_PM_MMCR0_PMC2_L2_INSTRUCTION_MISSES
Definition:
performancemonitor.h:61
OS_PM_MMCR0_PMC2_L1_SHARED_INTERVENTIONS
@ OS_PM_MMCR0_PMC2_L1_SHARED_INTERVENTIONS
Definition:
performancemonitor.h:71
OS_PM_MMCR0_PMC1_SLOW_L1_MISSES
@ OS_PM_MMCR0_PMC1_SLOW_L1_MISSES
Definition:
performancemonitor.h:43
OS_PM_MMCR0_PMC1_L2_SHARED_INTERVENTIONS
@ OS_PM_MMCR0_PMC1_L2_SHARED_INTERVENTIONS
Definition:
performancemonitor.h:47
OS_PM_MMCR0_PMC1_BIU_ADDRESS_ONLY_REQUESTS
@ OS_PM_MMCR0_PMC1_BIU_ADDRESS_ONLY_REQUESTS
Definition:
performancemonitor.h:50
OS_PM_MMCR0_PMC2_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR0_PMC2_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:56
OS_PM_MMCR0_PMC2_CIU_MODIFIED_INTERVENTIONS
@ OS_PM_MMCR0_PMC2_CIU_MODIFIED_INTERVENTIONS
Definition:
performancemonitor.h:74
OS_PM_MMCR0_PMC1_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR0_PMC1_TBL_RISING_TRANSITIONS
Definition:
performancemonitor.h:36
OS_PM_MMCR0_PMC1_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_DISPATCHED
Definition:
performancemonitor.h:37
OS_PM_MMCR0_PMC2_SLOW_OUTSTANDING_BIU_TRANSACTIONS
@ OS_PM_MMCR0_PMC2_SLOW_OUTSTANDING_BIU_TRANSACTIONS
Definition:
performancemonitor.h:73
OS_PM_MMCR0_PMC1_INSTRUCTIONS_EA_DELIVERED
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_EA_DELIVERED
Definition:
performancemonitor.h:41
OS_PM_MMCR0_PMC2_L2_SHARED_STORES
@ OS_PM_MMCR0_PMC2_L2_SHARED_STORES
Definition:
performancemonitor.h:70
OS_PM_MMCR0_PMC1_UNRESOLVED_STALL_CYCLES
@ OS_PM_MMCR0_PMC1_UNRESOLVED_STALL_CYCLES
Definition:
performancemonitor.h:45
OS_PM_MMCR0_PMC2_CURRENT
@ OS_PM_MMCR0_PMC2_CURRENT
Definition:
performancemonitor.h:54
OS_PM_MMCR0_PMC2_CPU_CYCLES
@ OS_PM_MMCR0_PMC2_CPU_CYCLES
Definition:
performancemonitor.h:55
OS_PM_MMCR0_PMC2_CACHE_SNOOPS
@ OS_PM_MMCR0_PMC2_CACHE_SNOOPS
Definition:
performancemonitor.h:65
OS_PM_MMCR0_PMC1_CACHE_PARADOXES
@ OS_PM_MMCR0_PMC1_CACHE_PARADOXES
Definition:
performancemonitor.h:48
OS_PM_MMCR0_PMC2_L1_ICACHE_MISSES
@ OS_PM_MMCR0_PMC2_L1_ICACHE_MISSES
Definition:
performancemonitor.h:59
OS_PM_MMCR0_PMC1_EIEIO_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR0_PMC1_EIEIO_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:38
OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED
Definition:
performancemonitor.h:35
OS_PM_MMCR0_PMC1_L1_SHARED_STORES
@ OS_PM_MMCR0_PMC1_L1_SHARED_STORES
Definition:
performancemonitor.h:46
OS_PM_MMCR0_PMC1_ITLB_SEARCH_CYCLES
@ OS_PM_MMCR0_PMC1_ITLB_SEARCH_CYCLES
Definition:
performancemonitor.h:39
OS_PM_MMCR0_PMC2_SYSTEM_UNIT_INSTRUCTIONS
@ OS_PM_MMCR0_PMC2_SYSTEM_UNIT_INSTRUCTIONS
Definition:
performancemonitor.h:67
OS_PM_MMCR0_PMC2_CIU_STORE_REQUESTS
@ OS_PM_MMCR0_PMC2_CIU_STORE_REQUESTS
Definition:
performancemonitor.h:72
OS_PM_MMCR0_PMC2_PRED_BRANCHES_NOT_TAKEN
@ OS_PM_MMCR0_PMC2_PRED_BRANCHES_NOT_TAKEN
Definition:
performancemonitor.h:62
OS_PM_MMCR0_PMC1_CURRENT
@ OS_PM_MMCR0_PMC1_CURRENT
Definition:
performancemonitor.h:33
OS_PM_MMCR0_PMC2_FIRST_SPECULATIVE_BRANCH_RESOLVES
@ OS_PM_MMCR0_PMC2_FIRST_SPECULATIVE_BRANCH_RESOLVES
Definition:
performancemonitor.h:69
OS_PM_MMCR0_PMC2_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR0_PMC2_INSTRUCTIONS_DISPATCHED
Definition:
performancemonitor.h:58
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