wut v1.8.0
Wii U Toolchain
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performancemonitor.h
Go to the documentation of this file.
1#pragma once
2#include <wut.h>
3
12#ifdef __cplusplus
13extern "C" {
14#endif
15
16
18typedef enum OSPerfMonArg {
19 OS_PM_ARG_MMCR0 = 1u << 0u,
20 OS_PM_ARG_MMCR1 = 1u << 1u,
21 OS_PM_ARG_PMC1 = 1u << 2u,
22 OS_PM_ARG_PMC2 = 1u << 3u,
23 OS_PM_ARG_PMC3 = 1u << 4u,
24 OS_PM_ARG_PMC4 = 1u << 5u,
26
32typedef enum OSPerfMonMMCR0Flags {
33 OS_PM_MMCR0_PMC1_CURRENT = 0b0000000u << 6,
34 OS_PM_MMCR0_PMC1_CPU_CYCLES = 0b0000001u << 6,
40 OS_PM_MMCR0_PMC1_L2_HITS = 0b0000111u << 6,
53
76
82typedef enum OSPerfMonMMCR1Flags {
83 OS_PM_MMCR1_PMC3_CURRENT = 0b00000u << 27,
104
105 OS_PM_MMCR1_PMC4_CURRENT = 0b00000u << 22,
125
142void OSSetPerformanceMonitor(uint32_t arg_mask,
143 uint32_t mmcr0,
144 uint32_t mmcr1,
145 uint32_t pmc1,
146 uint32_t pmc2,
147 uint32_t pmc3,
148 uint32_t pmc4);
149
153static inline
154uint32_t
156{
157 uint32_t result;
158 asm("mfupmc1 %[result]"
159 : [result] "=r"(result));
160 return result;
161}
162
166static inline
167uint32_t
169{
170 uint32_t result;
171 asm("mfupmc2 %[result]"
172 : [result] "=r"(result));
173 return result;
174}
175
179static inline
180uint32_t
182{
183 uint32_t result;
184 asm("mfupmc3 %[result]"
185 : [result] "=r"(result));
186 return result;
187}
188
192static inline
193uint32_t
195{
196 uint32_t result;
197 asm("mfupmc4 %[result]"
198 : [result] "=r"(result));
199 return result;
200}
201
202#ifdef __cplusplus
203}
204#endif
205
static uint32_t OSGetUPMC4()
Convenience function to read from UPMC4.
static uint32_t OSGetUPMC3()
Convenience function to read from UPMC3.
OSPerfMonArg
Used to tell OSSetPerformanceMonitor() which arguments are valid.
void OSSetPerformanceMonitor(uint32_t arg_mask, uint32_t mmcr0, uint32_t mmcr1, uint32_t pmc1, uint32_t pmc2, uint32_t pmc3, uint32_t pmc4)
Write to performance monitor registers.
static uint32_t OSGetUPMC1()
Convenience function to read from UPMC1.
static uint32_t OSGetUPMC2()
Convenience function to read from UPMC2.
OSPerfMonMMCR1Flags
Flags to write to (U)MMCR1 register.
OSPerfMonMMCR0Flags
Flags to write to (U)MMCR0 register.
@ OS_PM_ARG_MMCR0
@ OS_PM_ARG_PMC1
@ OS_PM_ARG_PMC2
@ OS_PM_ARG_PMC4
@ OS_PM_ARG_PMC3
@ OS_PM_ARG_MMCR1
@ OS_PM_MMCR1_PMC3_L1_DCACHE_MISSES
@ OS_PM_MMCR1_PMC3_SECOND_SPECULATIVE_BRANCH_RESOLVES
@ OS_PM_MMCR1_PMC3_L2_CACHE_OPERATIONS
@ OS_PM_MMCR1_PMC3_ICBI_SNOOPS
@ OS_PM_MMCR1_PMC3_BPU_STALL_LR_CR_CYCLES
@ OS_PM_MMCR1_PMC3_DTLB_MISSES
@ OS_PM_MMCR1_PMC3_L2_CASTOUTS_BY_SNOOPS
@ OS_PM_MMCR1_PMC3_FPU_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC3_CPU_CYCLES
@ OS_PM_MMCR1_PMC4_DTLB_SEARCH_CYCLES
@ OS_PM_MMCR1_PMC4_CIU_ARTRY_COUNT
@ OS_PM_MMCR1_PMC3_L1_LOAD_MISS_CYCLES
@ OS_PM_MMCR1_PMC4_L2_BANK_REFRESH_OVERFLOWS
@ OS_PM_MMCR1_PMC4_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC4_INTACT_COND_STORES_COMPLETED
@ OS_PM_MMCR1_PMC3_PRED_BRANCHES_TAKEN
@ OS_PM_MMCR1_PMC4_CIU_TWO_CORE_SHARED_INTERVENTIONS
@ OS_PM_MMCR1_PMC3_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC4_BRANCHES_MISPREDICTED
@ OS_PM_MMCR1_PMC3_L1_MODIFIED_INTERVENTIONS
@ OS_PM_MMCR1_PMC4_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR1_PMC4_L2_CASTOUTS
@ OS_PM_MMCR1_PMC3_CURRENT
@ OS_PM_MMCR1_PMC3_COND_STORES_COMPLETED
@ OS_PM_MMCR1_PMC3_L2_DATA_MISSES
@ OS_PM_MMCR1_PMC4_CURRENT
@ OS_PM_MMCR1_PMC4_CPU_CYCLES
@ OS_PM_MMCR1_PMC4_L2_MODIFIED_INTERVENTIONS
@ OS_PM_MMCR1_PMC4_TLBIE_SNOOPS
@ OS_PM_MMCR1_PMC4_BPU_STALL_TWO_BRANCHES_CYCLES
@ OS_PM_MMCR1_PMC3_BIU_LOAD_REQUESTS
@ OS_PM_MMCR1_PMC4_INTEGER_OPERATIONS
@ OS_PM_MMCR1_PMC3_CIU_SHARED_INTERVENTIONS
@ OS_PM_MMCR1_PMC3_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR1_PMC4_SNOOP_RETRIES
@ OS_PM_MMCR1_PMC4_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR1_PMC3_CIU_ADDRESS_ONLY_REQUESTS
@ OS_PM_MMCR1_PMC4_BIU_STORE_REQUESTS
@ OS_PM_MMCR1_PMC4_SYNC_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR1_PMC3_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR0_PMC1_CIU_PARADOXES
@ OS_PM_MMCR0_PMC2_RESERVED_LOADS
@ OS_PM_MMCR0_PMC1_CIU_LOAD_REQUESTS
@ OS_PM_MMCR0_PMC1_60XE_BUS_DATA_BEATS
@ OS_PM_MMCR0_PMC1_CPU_CYCLES
@ OS_PM_MMCR0_PMC1_L2_HITS
@ OS_PM_MMCR0_PMC2_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR0_PMC2_L1_TO_L2_CASTOUTS
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED_MATCHES_IABR
@ OS_PM_MMCR0_PMC2_LOADS_AND_STORES
@ OS_PM_MMCR0_PMC2_ITLB_MISSES
@ OS_PM_MMCR0_PMC1_UNRESOLVED_BRANCHES
@ OS_PM_MMCR0_PMC2_L1_INSTRUCTION_MISS_CYCLES
@ OS_PM_MMCR0_PMC2_L2_INSTRUCTION_MISSES
@ OS_PM_MMCR0_PMC2_L1_SHARED_INTERVENTIONS
@ OS_PM_MMCR0_PMC1_SLOW_L1_MISSES
@ OS_PM_MMCR0_PMC1_L2_SHARED_INTERVENTIONS
@ OS_PM_MMCR0_PMC1_BIU_ADDRESS_ONLY_REQUESTS
@ OS_PM_MMCR0_PMC2_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR0_PMC2_CIU_MODIFIED_INTERVENTIONS
@ OS_PM_MMCR0_PMC1_TBL_RISING_TRANSITIONS
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_DISPATCHED
@ OS_PM_MMCR0_PMC2_SLOW_OUTSTANDING_BIU_TRANSACTIONS
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_EA_DELIVERED
@ OS_PM_MMCR0_PMC2_L2_SHARED_STORES
@ OS_PM_MMCR0_PMC1_UNRESOLVED_STALL_CYCLES
@ OS_PM_MMCR0_PMC2_CURRENT
@ OS_PM_MMCR0_PMC2_CPU_CYCLES
@ OS_PM_MMCR0_PMC2_CACHE_SNOOPS
@ OS_PM_MMCR0_PMC1_CACHE_PARADOXES
@ OS_PM_MMCR0_PMC2_L1_ICACHE_MISSES
@ OS_PM_MMCR0_PMC1_EIEIO_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR0_PMC1_INSTRUCTIONS_COMPLETED
@ OS_PM_MMCR0_PMC1_L1_SHARED_STORES
@ OS_PM_MMCR0_PMC1_ITLB_SEARCH_CYCLES
@ OS_PM_MMCR0_PMC2_SYSTEM_UNIT_INSTRUCTIONS
@ OS_PM_MMCR0_PMC2_CIU_STORE_REQUESTS
@ OS_PM_MMCR0_PMC2_PRED_BRANCHES_NOT_TAKEN
@ OS_PM_MMCR0_PMC1_CURRENT
@ OS_PM_MMCR0_PMC2_FIRST_SPECULATIVE_BRANCH_RESOLVES
@ OS_PM_MMCR0_PMC2_INSTRUCTIONS_DISPATCHED